Intel leans more on RISC-V


No more uninvented here for the chip giant when it comes to processor architectures

Much like IBM after PC architecture fled and nearly collapsed Big Blue’s highly profitable minicomputer and mainframe business, Intel went through some soul-searching following Arm’s expansion of the world. from cell phones to just about everything else.

Intel went from being a company that relentlessly sued trying to keep control of the instruction set architecture (ISA) that powered the PCs that crippled IBM’s original business to a company that now sees or at least claims to see the benefits of an ISA that anyone can use to build their own processors. Intel is now one of RISC-V’s biggest fans, launching a program this week to try to get more chip designers involved in the architecture.

Speaking at RISC-V Spring Week in May, Gary Martz, Senior Director of Intel Foundry Services, said, “Serving the needs of the growing RISC-V community is one of our primary goals. We share the same vision that a free and open ISA, developed through broad industry collaboration, is needed… We want to help continue this work and that is why we are investing.

Intel is far from alone in trying to give RISC-V a hand. Storage company Western Digital was quick to adopt the ISA and provided its own processor design to the open-source community. Google sees RISC-V as the foundation for a new generation of accelerators capable of improving performance and reducing the intense power consumption of AI applications. And rather than trying to develop these accelerators himself – although he has experience with his own Tensorflow chips – he sees an open source community as vital to those ambitions. This has led Google to fund low-volume chip-making projects through US foundry SkyWater Technology, as well as developing its own tools to make it easier for those with more experience to design chips. software than hardware.

Microchip Technology, which struggled to break into the 32-bit market from its strong base of 8-bit and 16-bit microcontrollers, became a big fan of RISC-V. The acquisition of Microsemi, which itself absorbed Actel a few years earlier, made it easier for chip designers to prototype RISC-V designs in field-programmable gate arrays (FPGAs).

Intel also views the FPGA as a crucial technology to advance work on designs that incorporate RISC-V processor cores. The chipmaker bought Altera several years ago, incorporating the larger FPGAs into processor modules for data center users. Now, under the Pathfinder for RISC-V program launched on Tuesday (August 30, 2022), Intel is promoting FPGAs as prototyping vehicles for off-the-shelf processor cores and others in the program, such as Andes Technology, Chips Alliance, OpenHW Group and SiFive, have grown.

Much like Google, Intel has taken the approach that a friendly design environment for software developers is what is needed. “RISC-V adoption is at an inflection point across multiple markets and applications, and Intel fully understands that a healthy software ecosystem is essential for this new ISA to succeed,” said Vijay Krishnan, general manager of RISC-V. V ventures at Intel.

Pathfinder software is an integrated development environment (IDE) that incorporates tools from Intel itself as well as other vendors, such as UK-based Imperas Software, which provides an instruction set simulator to high speed so designs can be prototyped in a fully virtual domain environment before being moved to hardware. The company built a demo at the Design Automation Conference (DAC) where the simulator was able to run the Quake game on a reference model of a RISC-V processor core in more or less real time on a regular laptop computer.

Like Google, Intel even views hobbyists as potentially valuable. The Pathfinder IDE comes in two forms. The Starter Edition is aimed at hobbyists, academics and the research community and is available for free download. The most comprehensive professional edition is one that provides access to more cores and partner tools and will need to be licensed individually to commercial players.

With the rise of RISC-V, the question naturally arises as to whether Arm is in trouble. This doesn’t look good for the future given that accelerators are likely to become much more common in silicon due to their better power efficiency, assuming the software tools to program them work well. However, with this power comes responsibility. Existing kernel vendors such as Arm do extensive verification work on their designs to ensure kernels work under all circumstances.

Rupert Baines, marketing director of Codasip, points out that users who roll their own cores based on the open source ISA or who adopt the vendors’ RTL and then customize it have so far not always been so careful to check that the results works correctly. Although it can run a simple program very well, there are so many degrees of freedom in a CPU core that many bugs can hide and show up with a simple software change. Suppliers of finished kernels that aren’t custom can do a lot more to pre-check the design and ensure they work properly.

If a design team doesn’t need an accelerator tightly integrated with a host processor, something like an Arm Cortex will do just fine and may be easier to manage given that many engineers have experience with architecture. But unless the RISC-V community fires up, the direction of travel seems to become clearer. The one aspect of the design that can protect incumbents like Arm is that the CPU architecture itself becomes less important in determining overall system performance. It is much more how multiple processors interact with each other on an on-chip network or in the system. This is an area that still needs work.

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